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Anubhav Bhatla

First-year Ph.D. Student, EECS, MIT

Anubhav Bhatla

Cambridge, Massachusetts

CV Scholar Email

Hey! I am Anubhav, a first-year EECS Ph.D. student at the Massachusetts Institute of Technology with Prof. Mengjia Yan. I previously completed my Bachelors and Masters from the Department of Electrical Engineering, IIT Bombay, with Prof. Biswabandan Panda as my thesis advisor.

I am deeply interested in the research area of Computer Architecture, which involves a good mix of fascinating topics in Electrical Engineering and Computer Science. I am currently working on the reliability of accelerators against silent data corruptions, and have previously explored hardware security, designing cache structures to ensure security against various side-channel attacks.

Outside of academics, I enjoy going to the gym, reading books (mostly fiction) and playing sports such as tennis, squash, and badminton. I have also completed one year of training under the National Cadet Corps (NCC) at IIT Bombay.

Research Interests

Computer Systems & Architecture
Reliability
Hardware Security

In pursuit of these interests, I have been a part of the following research groups:

MATCHA — Microarchitecture Attacks and Challenges Group
Prof. Mengjia Yan · MIT
CASPER — Computer Architecture for Security and Performance Group
Prof. Biswabandan Panda · IIT Bombay
Memory Systems Lab
Prof. Moinuddin Qureshi · Georgia Tech
PACL — High-Performance Processor Architecture and Compilation Lab
Prof. Dean Tullsen · UC San Diego

News

Feb 6, 2026Check out our latest paper on a morphable secure cache design on arXiv!
Aug 13, 2025Our SoK work at USENIX Security 2025 won the Distinguished Artifact Award!
May 29, 2025Our SoK paper on secure randomized caches was accepted to USENIX Security '25.
all news →

Research

Building practical, secure, and reliable computer systems — from secure cache design to accelerator reliability and branch-predictor security.

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Reliability of Accelerators against SDCs

Understanding the reliability of state-of-the-art accelerators against silent data corruptions, and exploring the design space of mitigations.

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Understanding the Security of Secure Randomized Caches

Identifying security knobs in modern secure randomized caches and exploring their design space.

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Practical and Secure Cache Design at Ultra-Low Cost

The Avatar cache: a morphable LLC design which provides security-on-demand with minimal design complexity and ultra-low cost.

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Hardware-Efficient Secure Cache Design

The Maya Cache: a secure and storage-efficient fully-associative last-level cache design.

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Branch Predictor Partitioning for Performance

Optimizing the NOP padding algorithm and identifying hot branches to improve their prediction rates.

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Secure Cache-Line Reallocation

Preferentially re-allocating dead blocks for improving performance.

Anubhav's Blog

Hey, welcome to my blog. Stay tuned for interesting content here!

Publications

2025

  1. USENIX Sec
    SoK: So, You Think You Know All About Secure Randomized Caches?
    Anubhav Bhatla, Hari Rohit Bhavsar, Sayandeep Saha, and 1 more author
    Distinguished Artifact Award Winner
    PDF Code Slides Video

2024

  1. ISCA
    The Maya Cache: A Storage-efficient and Secure Fully-associative Last-level Cache
    Anubhav Bhatla, Navneet, and Biswabandan Panda
    PDF Code Slides

Projects

Teaching

Courses I have served as a Teaching Assistant for at MIT and IIT Bombay.

2025

CS773

Computer Architecture for Performance and Security

Prof. Biswabandan Panda · 100+ students

2025

EE789

Algorithmic Design of Digital Systems

Prof. Madhav Desai · 80+ students

2024

CS683

Advanced Computer Architecture

Prof. Biswabandan Panda · 100+ students

2024

EE229

Signal Processing

Prof. Preeti Rao · 90+ students

2022

EE309

Microprocessors

Prof. Virendra Singh · 200+ students

Academics

A catalogue of courses I have taken across my graduate and undergraduate studies.

MIT Courses

  • 6.591 - Secure Hardware Design
  • 6.512 - Formal Reasoning about Programs

Electives

Computer Systems

  • CS347 - Operating Systems
  • EE691 - Research and Development Project
  • EE748 - Advanced Topics in Computer Architecture

CV

Research Interests

Computer Systems & Architecture
Reliability
Hardware Security

Education

2025 - Present
Doctor of Philosophy
Massachusetts Institute of Technology
  • Ph.D. in Electrical Engineering and Computer Science
  • Advised by Prof. Mengjia Yan (MATCHA Group)
2020 - 2025
Bachelor + Master of Technology (Dual Degree)
Indian Institute of Technology Bombay
  • Integrated B.Tech + M.Tech in Electrical Engineering (GPA: 9.39/10)
  • Minor Degree in Computer Science and Engineering

Professional Experience

2023
Embedded Software Intern
Texas Instruments, Bangalore, India
  • Created a driver-monitoring application for the AM62Ax Sitara processor using GStreamer
  • Modified GStreamer pipelines to enable stacking of multiple DNN models
  • Created a boot loader porting guide for the Sitara AM62x processor

Mentorship

2025 - Present
Graduate Application Assistance Program (GAAP) Mentor
MIT EECS
2024 - 2025
Department Academic Mentor
Student Mentorship Program, IIT Bombay

Awards & Honours

  • Distinguished Artifact Award, USENIX Security Symposium (2025)
  • Intel India Research Fellowship 2024-25 (grant of INR 800,000)
  • Ranked 5th among 99 students in the EE Dual Degree program, IIT Bombay (2024)
  • Undergraduate Research Award, IIT Bombay (2023)
  • All India Rank 266 in JEE (Advanced) among 160,000+ candidates (2020)
  • KVPY Fellowship, All India Rank 337 (2018)

Skills

Languages

C, C++, VHDL, Verilog, Python, Assembly (8085), Algorithmic Assembly (Aa), Heptagon

Software

Intel Quartus, Vivado, Autodesk Fusion 360, GStreamer, Cadence Virtuoso, Synopsys Sentaurus, MATLAB, LTSpice, LaTeX

Simulators

ChampSim, gem5, Sniper, GPGPU-Sim, CacheFX, PCACTI